Responsibilities: Sr. Customer Quality Manager to be a primary point of contact for customers regarding all aspects of image sensor quality. Primary focus will be customers in the automotive market. Have following responsibilities Supporting customers with initial return
職種 正社員 職務明細 You will be responsible for the development of a software platform (Edge AI Platform) that utilizes AI and Sonys image sensors. Edge AI Platform development consists of AI application development that utilizes Sonys image sensors, software platform
職種 正社員 職務明細 ミドクラについて 高速分散 DB「ダイナモ」の開発者やアマゾン初期のアーキテクトを担った天才エンジニアとともに 2010 年 1 月に真のグローバルテックスタートアップとして産声をあげたミドクラは、2019 年 6 月よりソニーグループの一員として、ミドクラの持つ分散コンピューティング技術/仮想化技術、ソニー の持つ先進センサー技術との融合を目指して、GAFA 対抗の次世代 Edge AI Platform 構築に挑んでい ます。 東京/バルセロナ/ローザンヌに研究開発拠点を持ち、元アマゾン/グーグル/マイクロソフトなどの 腕に覚えのあるエンジニアが世界中から参集(国籍は 10 ヵ国以上)、世界最先端を行く技術企業と の協業やローザンヌ工科大学等の研究機関とのコラボレーションなどを通じて、日々ビジョン達成に 向けて邁進をしている真にグローバルな企業です。 なぜやるのか 全てが繋がる IoT の時代、ビッグデータ解析による AI の時代と言われて久しいですが、AI アプリケ ーションの開発は一朝一夕にはいかない多大な労力を要するものとなっています。一方、企業におい ては、自社が保有する、あるいは創り出すデータを価値あるものとして、AI 利用によるサービスビ
Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring
• Communicate proactively with other disciplines and take on Technical Leadership Role to develop Chip top and Blocks thoroughly from specification, design, verification and production support • Define chip top development plan based on product features
Job responsibilities: • Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis) • Define ISP HW Architecture based on product features and performance requirements, also with gate count and power
Responsibilities: Responsible for RTL design and verification using Verilog and System Verilog Define System Architecture and/or Block level Micro Architecture based on product features and performance requirements, also with gate count and power estimation Work closely
Responsibilities: Execute characterization, measurements, debug, analysis for CMOS image sensors Provide design characterization report, presentation, technical information in timely manner Provide technical solutions and/or tunings to deliver optimum settings for sensor operations Communicate proactively with other disciplines and take
• Define System Architecture of array readout circuit based on product features and performance requirements. • Work closely with digital, layout, process, evaluation engineers to debug, optimize performance of image sensors and successfully bring new products from initial
Responsibilities: Responsible for the following items in CMOS Image Sensors pixel characterization work: Test and evaluate the pixel characteristics of CIS. Provide appropriate reports and feedback to related departments such as design, Application Engineering, Product Engineering etc. Developing
Responsibilities: Schedule a characterization/testing plan and work with R&D teams and manufacturing engineers to resolve different technical issues, in order to meet performance requirements. Participate in product definition and provide DFM inputs. Work in close collaboration
Responsibilities: Develop advanced CIS technologies and lead project through detailed process and process integration knowledge. Complete the project from NTO to risk mass production phase to meet all PRD targets and enough yield/qualification evidence. Work with
Responsibilities: Pixel circuit and photodiode design as discussing with process integration group, modeling group, characterization group and peripheral circuit group. Achieve best pixel performance with optimization among photodiodes and pixel circuit. Analyze pixel performance problems as
Responsibilities: The imaging algorithm engineer will apply knowledge of image sensor and camera system to, scientifically, analyze key performance of OmniVision’s products and provide technical suggestions of improvement. Conduct analytic studies of fundamental performance issues for CIS or
