Senior Design Verification (DV) / Digital Engineer

Summary

Posted: Feb 2, 2025
Role Number:
200589523
Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hard-working and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next groundbreaking Apple product!The people at Apple don’t just create products; they create the kind of wonder that has revolutionized entire industries. The diversity of their people and their ideas fuels the innovation that permeates everything we do, from groundbreaking technology to industry-leading environmental initiatives. Join Apple and contribute to making the world a better place. Imagine the impact you could make here. The Apple Japan Design Center is currently seeking a highly motivated and talented Design Verification Engineer to join our exceptional team!

Description

- You will review design and architecture specifications.- You will understand the functional & performance goals of the design and you use this knowledge to test effectively.- You will communicate and collaborate with digital design, analog design, architecture and firmware teams to understand use cases and corner conditions.- You will develop test plans and coverage plans.- You will work closely with team members and cross-functional teams to execute on verification plans.- You will have the responsibility for construction of verification environments, coding of test scenarios and assertions.- You will write scripts to help with automation and data analysis.- You will run and triage regressions, track bugs, and analyze coverage to achieve quality results.

Minimum Qualifications

BS/MS required.
Minimum of 7 years of relevant experience
Knowledge of Verilog/SystemVerilog, digital simulation and debug
Knowledge of computer architecture and digital design fundamentals
Strong skills in SystemVerilog with experience crafting verification environments using UVM
Experience with end-to-end process for SoC digital verification – block and top-level test-planning, constrained random testing, writing and closing coverage
Experience with Perl, Python or similar scripting language
Strong problem solving and analytical skills
Strong communication skills
Ability to work independently to complete project goals

Preferred Qualifications